Dolphin Design Selects Imperas for Processor Functional Design Verification

ImperasDV processor verification solutions enable ‘step-compare’ advanced functional verification including asynchronous events, plus verification IP reusability with RVVI

Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced that ImperasDVTM has been adopted by Dolphin Design for RISC-V processor verification for the Panther DSP/AI Accelerator IP from Dolphin Design. ImperasDV, with ‘step-compare’ methodology, is the state-of-the-art approach for processor design verification including asynchronous events.

The open standard ISA (Instruction Set Architecture) of RISC-V offers processor developers many options and configurable features, in addition to the supporting tools and software, this combination offers both design flexibility and ecosystem compatibility. ImperasDV supports the RISC-V design verification tasks across the complete specification with the Imperas golden reference model, architectural validation tests, additional functional test suites, coverage analysis, and simulation-based test methodologies for asynchronous events and debug operations.

The open standard RVVI (RISC-V Verification Interface) provides the essential guidelines for the infrastructure around the processor testbench that supports the growing ecosystem of Verification IP for RISC-V processor verification. The RVVI open standard and methodology is based on an open specification (https://github.com/riscv-verification/RVVI), and can be adapted to any configuration permitted within the RISC-V specification. In adopting the RVVI standard, developers can leverage all the common components off the shelf and explore additional options with reusable verification IP across projects.

“Our verification methodology for the Panther DSP/AI Accelerator IP needs to address not just the full range of the current configuration options but also the roadmap for Panther,” said Philippe Berger, CEO of Dolphin Design. “ImperasDV is the cornerstone of our simulation-based DV strategy, with the Imperas golden reference model, scoreboard, verification IP, functional coverage analysis and debug efficiency.”

“In complex compute systems the processor core may be complemented with additional accelerators or combined in multicore arrays to address the application workloads,” said Simon Davidmann, CEO at Imperas Software Ltd. “RISC-V processor verification is always important, but this is especially true with complex structures that may present the processor core with unusual scenarios not encountered in traditional embedded designs. ImperasDV supports the sophisticated DV methodologies such as ‘lock-step-compare’ and asynchronous events that are required for today’s advanced cores and multi-processor platforms.”

Availability

The RVVI (RISC-V Verification Interface) specification is available at https://github.com/riscv-verification/RVVI.

The ImperasDV RISC-V processor verification technology is already in active use with many leading customers, some of which have working silicon prototypes and are now working on 2nd and even 3rd generation designs. These customers, partners and users span the breadth of RISC-V adopters from open source to commercial; research to industrial; microcontrollers to high performance computing. A select sample of these include – Codasip, Dolphin Design, EM Microelectronics (Swatch) , Frontgrade Gaisler, Intrinsix, NSITEXE (Denso) , Nvidia Networking (Mellanox) , NXP, OpenHW Group, MIPS, Seagate Technology, Silicon Labs, and Valtrix Systems, plus many others yet to be made public.

ImperasDV is available now, additional details are available at Imperas.com/ImperasDV.

The free riscvOVPsimPlus package, including the Imperas RISC-V Reference Model, sample test suites and instruction coverage analysis, including updates for the latest RISC-V ratified specifications is also available on OVPworld at www.ovpworld.org/riscvOVPsimPlus.

Imperas at the RISC-V Summit Europe

Imperas is presenting a keynote talk on RISC-V processor verification at the RISC-V Summit Europe June 5-9 in Barcelona. Additionally, Imperas is presenting a paper on “Hybrid Simulation with Emulation for RISC-V Software Bring Up and Hardware-Software Co-Verification,” as well as two poster papers. Attendees can also talk to Imperas engineers at the exhibit booth at the Summit.

https://riscv-europe.org