Silicon Labs selects Imperas RISC-V Reference Model for verification

RISC-V processor verification using SystemVerilog UVM test bench with step-and-compare between reference and RTL for dynamic testcase scenarios with coverage analysis

Oxford, United Kingdom, December 8th, 2020 — Imperas Software Ltd., the leader in RISC-V processor verification technology, today confirmed the selection by Silicon Labs (NASDAQ: SLAB) of the Imperas RISC-V reference model as part of their RISC-V processor verification work. RISC-V processor verification can be the most complex of tasks within an SoC verification plan and to address the flexibility and configurability of RISC-V it is important that the reference model supports user and privilege modes plus all the standard ratified RISC-V specification variant options. In addition, to support the chip design schedules the refence model also needs to maintain configurability options for all the specification subset references as a dependable golden reference model for verification over the full lifetime of the project design phase and support future software development.

One of the attractive options of the open standard RISC-V ISA is the potential to extend or modify the base features into a unique design solution. Adopting a well verified existing open-source RISC-V core IP as a solid and stable starting point is an approach that offers several advantages over a completely fresh development just stating from the open standard RISC-V ISA specification. Clearly any new modification or extension will require detailed analysis and testing, but in the case of a processor cores care must also be taken not to affect any underlying functionality or introduce unintended consequences The Imperas SystemVerilog encapsulated golden reference model supports step-and-compare verification which is essential to address the testcase scenarios associated with dynamic asynchronous events and debug mode operations. These deliverables are a starting point for adopters to expand and extend the verification plan along with the new core modifications or extensions which may be kept private or shared with others.

“Silicon Labs selected Imperas simulation tools and RISC-V models for our design verification (DV) flow because of the quality of the models and the ease of use of the Imperas environment,” said Sebastian Ahmed, Senior Director of R&D at Silicon Labs. “The Imperas golden reference model of the RISC-V core and their experience with processor RTL DV flows were also critical to our decision.”

“Clear differences exist between many aspects of open-source projects and commercial processor IP, but a common thread in all projects is the desire for adoption and successful implementation in silicon devices,” said Simon Davidmann, CEO at Imperas Software Ltd. “Successful implementation for any RISC-V core ultimately relies on the quality of its verification. By including the Imperas RISC-V golden reference model in their advanced SystemVerilog UVM test environment, Silicon Labs can verify their design with confidence.”