QDPAK and Low-profile TO247 in the latest GeneSiC™ 5th Generation Trench-Assisted Planar SiC MOSFET technology deliver significant improvements in performance and lifetime for AI data centers, grid and energy infrastructure, and industrial electrification with voltage ratings of 1200 V.
TORRANCE, CA – March 11th, 2026 — Navitas Semiconductor (Nasdaq: NVTS), an industry leader in next-generation GaNFast™ gallium nitride (GaN) and GeneSiC™ silicon carbide (SiC) power semiconductors, today announced the launch of two new packages: top-side cooled QDPAK and a low-profile TO-247-4L with asymmetrical leads in its 5th generation GeneSiC™ technology platform. The latest 1200 V SiC MOSFET products set a new industry benchmark for power density and ruggedness.
5th generation Trench-Assisted Planar (TAP) technology
This technology delivers 35% improvements in RDS,ON × QGD figure of merit (FoM), and about 25% improvement in QGD / QGS ratio. When coupled with stable high threshold voltage, VGS,TH, of >3 V, this technology ensures immunity against parasitic turn-on, providing a robust and predictable switching performance.
Top-side cooled (TSC) QDPAK
The QDPAK package is designed to overcome the thermal limitations of conventional PCB cooling by enabling heat dissipation directly through the top of the package to the heatsink. This optimized thermal path significantly improves heat dissipation efficiency and enables smaller system footprints. The package also minimizes parasitic inductance, supporting cleaner switching and higher efficiency at high frequencies. In addition, the QDPAK platform supports larger die sizes and higher current capability, facilitating the ultra-low RDS(ON) values for high-power applications, while its compact surface-mount profile enables scalable high-volume automated assembly.
- Compact footprint: Features a 15 mm x 21 mm area with an ultra-low height of only 2.3 mm.
- Enhanced creepage: Optimized with a groove in the package mold compound that extends creepage to 5 mm without trading off the area of the exposed top-side thermal pad.
- High-voltage integration: Supports up to 1000 VRMS applications with an epoxy molding compound (EMC) featuring a Comparative Tracking Index (CTI) of >600.
- Thermal integration: Designed for easier system-level thermal integration via top-side cooling.
Low-profile TO-247-4-LP
The low-profile TO-247-4-LP through-hole package variant is an optimized package for power electronics systems where vertical clearance is limited, such as high-density AI power racks. By minimizing the height of the package on the PCBA, this package enables higher power density when compared with systems made with a standard TO-247-4 package.
- Density optimized: Provides a reduced vertical footprint on the PCBA to support compact form-factor requirements where conventional TO-247-4 package height is a constraint.
- Manufacturing precision: Optimized with asymmetrical leads (thin leads for gate and Kelvin-source) to improve PCBA manufacturing tolerances.
- AI Data Center ready: Specifically targeted at applications like AI data center power supplies, where form-factor and maximum allowable height are critical.
“Our customers are pushing the boundaries of what is possible in AI data center and energy infrastructure applications,” said Paul Wheeler, VP & GM of the SiC business unit at Navitas. “The introduction of top-side cooled QDPAK, and low-profile TO-247-4-LP packages is a direct response to the need for ‘more power in less space’”.
A white paper on the Trench-Assisted Planar technology is available for free download from the Navitas website.
|
Part Number
|
Package
|
VDS (V)
|
RDS,ON (mΩ)
|
|
G5R06MT12QP
|
QDPAK
|
1200
|
6.5
|
|
G5R12MT12QP
|
QDPAK
|
1200
|
12
|
|
G5R06MT12LK
|
TO-247-4-LP
|
1200
|
6.5
|
|
G5R12MT12LK
|
TO-247-4-LP
|
1200
|
12
|
For further information, please visit –
- Navitas GeneSiC MOSFETs: https://navitassemi.com/genesic-mosfets-products/
- 5th Generation Trench-Assisted Planar (TAP) SiC MOSFET technology: https://navitassemi.com/navitas-unveils-5th-generation-sic-trench-assisted-planar-tap-technology/
To request samples, please contact a Navitas representative or write to info@navitassemi.com.
*Navitas uses the term ‘AEC-Plus’ to indicate parts exceeding AEC-Q101 and JEDEC standards for reliability testing based on Navitas test results.
![](https://www.semiconductorforu.com/wp-content/uploads/2025/03/2020-Battery_KE1010R2-970x250-ROTATING-FINAL-V3.gif")
