Imperas RISC-V reference models, simulator, tests, and verification IP in combination with Cadence SystemVerilog simulation tools provide a unified RISC-V verification solution
Oxford, United Kingdom, July 10th, 2023 — Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Cadence Design Systems, Inc. (Nasdaq: CDNS) has collaborated with Imperas to enable NSITEXE, Inc., a group company of the DENSO Corporation, in the development of RISC-V-based processor IP for functional safety and next-generation embedded systems. The ImperasDV RISC-V processor verification solution is fully compatible with the complete Cadence verification flow, including the Xcelium Logic Simulator and Verisium Artificial Intelligence (AI)-Driven Platform for debug, analysis and management.
ImperasDV is a RISC-V processor verification solution based on the industry-leading lock-step continuous compare methodology. It enables both accurate detection of issues and the efficient resolution of discrepancies between the design under test and the Imperas RISC-V Reference Model. The Cadence Xcelium Logic Simulator provides the SystemVerilog simulation environment, including the tightly-integrated, high-performance interface required to work with ImperasDV effectively. These are used with the Cadence SimVision Debug and analysis tools to create a unified environment for comprehensive verification of the NSITEXE Akaria processor IP, including the NS72, which is an out-of-order 64-bit RISC-V processor with the RVV vector extension.
RISC-V, with its open-standard Instruction Set Architecture (ISA), offers processor developers many options and configurable features, enabling the development of optimized domain-specific processors. ImperasDV supports the RISC-V design verification tasks across the complete specification, plus custom instructions, with the Imperas RISC-V reference model, architectural validation tests, additional functional test suites, coverage analysis, and simulation-based test methodologies for asynchronous events and debug operations.
“The NSITEXE Akaria processors, developed with the use of Imperas RISC-V verification technology and the leading-edge SystemVerilog simulator and debug tools from Cadence, are targeted to address the high-performance requirements for AI and automotive requirements. The Akaria processors include the necessary features and quality to achieve the ISO 26262 ASIL D functional safety standard, in addition to being optimized and efficient processors for the next-generation embedded applications,” said Hideki Sugimoto, CTO of NSITEXE, Inc., a group company of DENSO Corporation. “As the NSITEXE Akaria processors are adopted across a wide range of next-generation automotive, safety-critical, and embedded applications, the verification methodology with the support from Imperas and Cadence has been invaluable in achieving our quality goals and on-time development schedule.”
“By integrating our Xcelium Logic Simulator with Imperas’s RISC-V verification technology, we’ve empowered NSITEXE to design the next-generation of its Akaria processors, which are optimized for safety-critical applications and compliant with the ISO 26262 ASIL D standard,” said Paul Cunningham, general manager of the System & Verification Group at Cadence. “Our work together exemplifies Cadence’s commitment to collaboration and innovation to support our customers in the rapidly evolving semiconductor industry.”
“Processor verification is challenging, and yet critical to RISC-V adoption,” said Simon Davidmann, CEO at Imperas Software Ltd. “ImperasDV is the first commercially available RISC-V processor verification solution, and the achievement of the tight integration with Cadence is key to the successful use of ImperasDV by NSITEXE.”
Case Study Now Available
Cadence, Imperas, and NSITEXE have released more detail on the design flow and implementation of the lock-step continuous compare RISC-V verification methodology as a case study. The case study describes the NSITEXE RISC-V processor IP, including the verification challenges of the NS72 architecture, the lock-step continuous compare verification methodology being used for processor DV, and examples of bugs that were avoided by using this method. The case study describes the integration between Imperas and Cadence tools used and details of the full verification flow.
The case study is available now at https://www.imperas.com/docs.
The ImperasDV RISC-V processor verification technology is already in active use with many leading customers, some of whom have working silicon prototypes and are now working on second-generation designs. These customers, partners, and users span the breadth of RISC-V adopters from open source to commercial, research to industrial, and microcontrollers to high-performance computing. A select sample of these includes Codasip, Dolphin Design, EM Microelectronics (Swatch), Frontgrade Gaisler, Intrinsix, NSITEXE (Denso), NVIDIA Networking (Mellanox), NXP, OpenHW Group, MIPS, Seagate Technology, Silicon Labs, and Valtrix Systems, plus many others yet to be made public. ImperasDV is available now, and more details are available at Imperas.com/ImperasDV.
The RISC-V Verification Interface – RVVI
To help leverage the investment in verification IP and test infrastructure, the open-standard RISC-V Verification Interface (RVVI) has been adopted by many commercial developers and open-source projects, such as the OpenHW projects within the roadmap of CORE-V IP cores. RVVI provides a standard interface for connecting RISC-V processor RTL to a testbench via a tracer. It also defines a standard API for RISC-V verification IP that supports the lock-step continuous compare methodology. The RVVI flexibility supports the full range of RISC-V specifications and features and can be adopted with increasing levels of capability for designs with privilege modes, vector extensions, out-of-order pipelines, multi-threading, multi-hart, multi-issue, plus user-defined custom instructions and extensions. RVVI supports the innovation of RISC-V with the flexibility required for verification IP and reuse as DV teams scale up to support the rapid growth in RISC-V verification projects. See https://github.com/riscv-verification/RVVI for more information and to download.
The free riscvOVPsimPlus package, including the Imperas RISC-V Reference Model, latest test suites, and instruction coverage analysis, including updates for the latest RISC-V-ratified specifications is now available on OVPworld at www.OVPworld.org/riscvOVPsimPlus.
DAC 2023 – July 9-13 2023, San Francisco, California
Please visit Cadence (Booth 1511) and Imperas (Booth 2336) during DAC 60 for demonstrations and discussions.