Imperas Collaborates with Synopsys on SystemVerilog based RISC-V Verification

ImperasDV™ verification solutions are now certified for use with Synopsys functional simulation and debug tools with ‘lock-step-compare’ for RISC-V processor verification

Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced a collaboration with Synopsys, Inc. to address the growing demand for RISC-V processor verification. This collaboration enables mutual customers to streamline their RISC-V verification tasks using ImperasDV verification solutions and Synopsys’ industry-leading VCS® simulation and Verdi® debug tools for improved efficiency to achieve critical time-to-market and quality objectives. ImperasDV is the first commercially available verification IP for RISC-V processors including architectural validation test suites that are important for RISC-V developers to ensure hardware implementations are in line with the expectations of the software ecosystem supporting RISC-V. It has native support for the open standard RISC-V Verification Interface (RVVI) and uses a ‘lock-step-compare’ co-simulation methodology for comprehensive processor verification including asynchronous events and debug operations.

The RISC-V open standard ISA provides the framework for optimized processors targeted at application solutions in new and creative ways. In addition, design teams can utilize the new flexibility across all aspects of an SoC project with implementations targeted at internal control and management functions for power, security, communications and other tasks beyond the scope of a limited state machine. RISC-V is also revolutionizing the High-Performance Computing (HPC) design space with multicore arrays, vector accelerators, and complex pipelines featuring superscalar, out-of-order, multi-issue, and hardware multithreading, to name but a few of the techniques presented at technical conferences recently.

The new design freedoms of RISC-V are resulting in a growing consensus across the SoC community that RISC-V verification requirements need to be integrated into SoC schedules and planning. While processor verification may not be entirely new, RISC-V represents a massive shift in verification responsibility which in turn highlights the necessity for efficient verification to achieve key tape-out milestones and time-to-market targets. Any successful verification plan can be summarized as high-quality stimulus to achieve the coverage targets. The combination of Synopsys VCS simulation and ImperasDV provides a seamless integration of testbench, processor RTL, and ImperasDV verification solutions in a combined SystemVerilog environment for ‘lock-step-compare’ co-simulation between the RTL design under test (DUT) and the Imperas RISC-V processor reference model. With this close integration, the debug at the point of discrepancy can be easily explored with a friction-free transition between the Verilog RTL and the Imperas RISC-V reference model using Synopsys Verdi and the Imperas eGui.

“RISC-V adoption is growing across key market segments as SoC teams explore the flexibility of an open standard ISA for optimized processors,” said Kiran Vittal, senior director of Partner Alliances Marketing for Synopsys EDA Group. “Our collaboration with Imperas, leveraging Synopsys’ leading simulation and debug solutions, enables our mutual customers to address verification complexities for RISC-V processor cores and quickly achieve coverage convergence.”

“Simulation is the foundation supporting all of the semiconductor industry for design and verification,” said Simon Davidmann, CEO at Imperas Software Ltd. “The Imperas reference models and simulation technology are structured for close integration within co-simulation and emulation environments. With this latest collaboration with Synopsys, our mutual customers can leverage all the advantages of the ImperasDV verification solutions with the advanced innovations in Synopsys VCS high performance simulation and Verdi debug platform for a complete SystemVerilog ‘lock-step-compare’ flow with efficient debug for RISC-V verification.”

Synopsys VCS, Synopsys Verdi and ImperasDV applications note

To outline the flow for RISC-V processor verification this application note covers the key steps of using ImperasDV RISC-V Verification IP with Synopsys VCS and Verdi debug solutions. Topics include:

• Introduction to Imperas and RISC-V verification methodology
• Introduction to ImperasDV
• Integrating ImperasDV with a SystemVerilog testbench
• RISC-V test programs
• Running a simulation using ImperasDV and VCS
• Debugging using Verdi and Imperas MPD eGui
• Functional coverage: riscvISACOV and Verdi

The applications note is available now, please e-mail requests to info@imperas.com.

DVCon 2023 (February 27 to March 2, 2023), San Jose, California

Please visit Synopsys (Booth #105-107) and Imperas (Booth #108) for demonstrations and discussions.

For more details see https://dvcon.org to see all the sessions hosted by Imperas and Synopsys.

About the RISC-V Verification Interface (RVVI)

The open standard RVVI provides a common methodology for the key components of the testbench to connect between the RTL instruction tracer and reference models to fully support the ‘lock-step-compare’ verification approach. The RVVI flexibility supports the full range of RISC-V specifications and features and can be adopted with increasing levels of capability for designs with privilege modes, vector extensions, out-of-order pipelines, multi-threading, multi-hart, multi-issue, plus user-defined custom instructions and extensions. RVVI supports the innovation of RISC-V with the flexibility required for verification IP and reuse as DV teams scale up to support the rapid growth in RISC-V verification projects. See https://github.com/riscv-verification/RVVI for more information and to download.

Availability

ImperasDV is available now, more details are available at https://www.imperas.com/ImperasDV.