Meets the most demanding requirements of tomorrow’s test and measurement, and defense applications
DALLAS and INDIA (May 23, 2019) – Texas Instruments (TI) (NASDAQ:TXN) today introduced a new ultra-high-speed analog-to-digital converter (ADC) with the industry’s widest bandwidth, fastest sampling rate and lowest power consumption. The ADC12DJ5200RF helps engineers achieve high measurement accuracy for 5G testing applications and oscilloscopes, and direct X-band sampling for radar applications. For more information, see www.ti.com/ADC12DJ5200RF-pr.
Achieve the fastest measurements across the widest frequency spectrum
· Widest bandwidth: At 8 GHz, the ADC12DJ5200RF enables engineers to achieve as much as 20% higher analog input bandwidth than competing devices, which gives engineers the ability to directly digitize very high frequencies without the power consumption, cost and size of additional down-conversion.
· Fastest 12-bit ADC: In dual-channel mode, the ADC12DJ5200RF samples at 5.2 gigasamples per second (GSPS) and captures instantaneous bandwidth (IBW) as high as 2.6 GHz at 12-bit resolution. In single-channel mode, the new ultra-high-speed ADC samples at 10.4 GSPS and captures IBW up to 5.2 GHz.
· Efficient interface: As the first standalone GSPS ADC to support the JESD204C standard interface, the ADC12DJ5200RF helps minimize the number of serializer/deserializer lanes needed to output data to field-programmable gate arrays (FPGAs), enabling designers to achieve higher data rates.
Design with the highest performance and stability across power supply and temperature variations
· Highest signal detection sensitivity: The ADC12DJ5200RF has the highest available dynamic performance across power-supply variations, even at minimum specifications, which improves signal intelligence by providing ultra-high receiver sensitivity to detect even the smallest and weakest signals. In addition, the device includes internal dither which improves spurious-free performance.
· High measurement accuracy: TI’s new ultra-high-speed ADC greatly minimizes system errors with offset error as low as ±300 µV and zero temperature drift.
· Lowest CER: Engineers designing test and measurement equipment can achieve high measurement repeatability by taking advantage of the extremely low code error rate (CER) of the ADC12DJ5200RF, which is more than 100 times better than competing devices.
Reduce solution size by 30% and achieve 20% lower power consumption
· Smaller design footprint: At 10 mm by 10 mm – 30% smaller than discrete solutions – the ADC12DJ5200RF helps engineers save board space. This new ultra-high-speed ADC also requires a reduced number of lanes, which further allows for a smaller printed circuit board design.
· Lowest power consumption: Engineers can minimize heat dissipation and simplify overall thermal management in their designs with the ADC12DJ5200RF 4-W power consumption, 20% lower than competitive ADCs.
The ADC12DJ5200RF is pin-compatible with the following other TI GSPS ADCs to provide an easy upgrade path from 2.7 GSPS to 10.4 GSPS, and minimizes the time and cost of redesign: ADC12DJ3200, ADC12DJ2700 and ADC08DJ3200.
Tools and support to speed design
· Test the new ultra-high-speed ADC with the ADC12DJ5200RFEVM and TSW14J57EVM evaluation modules, available today from the TI store and authorized distributors.
· Engineers can jump-start their designs using the ADC12DJ5200RF with the “Multichip synchronization reference design for clocking and power supply optimization.”
Availability and packaging
The ADC12DJ5200RF dual- and single-channel ultra-high-speed ADC is available for sampling through the TI store. The device is in a 144-ball, 10-by-10-mm flip-chip ball grid array (FCBGA) package.