In general, power MOSFETs employ thicker oxides, deeper junctions and have longer channel lengths. These generally post a penalty on device performance such as transconductance (gm) and speed (fT). Nevertheless, power applications from MOSFETs have been on the rise, for example, due to the increasing demand of cellular phones and cellular base stations which require extra high voltage.
Power MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors) are three terminal silicon devices that function by applying signal to the gate that controls current conduction between source and drain. Their current conduction capabilities are up to several tens of amperes with breakdown voltage rating of 10V to 1000V.
DMOS (Double-Diffused MOS)
As the name implies, in the DMOS transistor the channel length is determined by the higher diffusion rate of the P-doping compared to the N-doping of the source. The p-diffusion serves as channel doping and has good punch through control. The channel is followed by a lightly doped n- – drift region.
This drift region is long compared to the channel, and it minimizes the peak electric field in this region by maintaining a uniform field. Usually the drain is located at the substrate contact. The field near the drain is the same as in the drift region , so multiplication, avalanche breakdown and oxide charging are less compared to conventional MOSFETs.
LDMOS (Laterally Diffused MOS)
The LDMOS has a lateral current flow pattern which is major difference from DMOS. The drift region here is an implanted horizontal region. Such a horizontal arrangement enables thin- substrate to deplete this drift region at high drain bias. In low drain bias its higher doping gives lower series resistance.
Drift region behaves like nonlinear resistor. Its resistance determined by 1/nqµ at low drain bias. At high drain bias, the region is fdly depleted so a large voltage drop can be supported this concept called Reduce Surface Field (RESURF) technology.