Imperas RISC-V reference models, simulator, tests, and verification IP are supporting Ventana Micro in delivering a performance-leading family of data center class CPU cores
Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Ventana Micro Systems Inc., a leader in high-performance RISC-V processors and RISC-V International Premier Member, has selected Imperas simulation and test and verification solutions for the RISC-V processors under development as IP cores and chiplets.
Ventana delivers the highest performance RISC-V CPUs with domain specific workload acceleration capability delivered in the form of multi-core chiplets or core IP for high-performance applications in the data center, automotive, 5G infrastructure, AI, and client markets. Ventana was founded by processor industry veterans, and is a member of the RISC-V International Board of Directors and its Technical Steering Committee.
Imperas provides a flexible framework for RISC-V processor verification that enables design verification teams to fully verify a processor implementation and accelerate time to market. Based on the trusted Imperas RISC-V reference models, verification IP, and Imperas architectural validation tests, Imperas also offers the dynamic comparisons of the processor implementation against the Imperas RISC-V reference model in a ‘lock-step-compare’ methodology which provides both accurate detection of issues, and the efficient resolution of bugs.
The verification of an implementation of the RISC-V Vector specification can be complex due to the wide range of configuration options and parameters available to developers. The Imperas RISC-V reference models include the provisions to cover the complete envelope of the Vector specification. To complement this, the Imperas verification IP includes architectural validation tests test suites for vectors, available on request and configured to the same target parameters. The free riscvOVPsimPlus package includes a complete Imperas RISC-V reference model and architectural validation test suite, configured for a base vector engine of RV32GCV with elen:32, vlen:256, slen:256.
“At Ventana, our teams of developers are building the foundational processor IP and chiplet building blocks that will enable a step change in performance for the most demanding compute workload markets,” said Josh Scheid, Head of Design Verification at Ventana Micro Systems Inc. “Our verification strategy is to exercise the RISC-V based processors across the most demanding scenarios and are using Imperas RISC-V vector test suites in addition to the Imperas golden reference model in our verification environment.”
“Often design innovation is focused on the initial concept or spark of an idea, but implementing a state-of-the-art processor based on the open standard specification of RISC-V is more about the dedicated engineering behind the development and test with bringing a project concept to design completion,” said Simon Davidmann, CEO at Imperas Software Ltd. “RISC-V offers a new era of design flexibility, at Imperas we develop verification solutions to complement the verification task with a flexible framework that expert verification teams can extend and adapt as they build the processors of tomorrow. We are excited to be selected by the innovators at Ventana Micro for the verification tasks.”
The ImperasDV RISC-V processor verification technology is already in active use with many leading customers, some of which have working silicon prototypes and are now working on 2nd generation designs. These customers, partners, and users span the breadth of RISC-V adopters from open source to commercial; research to industrial; microcontrollers to high-performance computing. A select sample of these includes – Codasip, Dolphin Design, EM Microelectronics (Swatch), Frontgrade Gaisler, Intrinsix, NSITEXE (Denso), Nvidia Networking (Mellanox), NXP, OpenHW Group, MIPS, Seagate Technology, Silicon Labs, and Valtrix Systems, plus many others yet to be made public. ImperasDV is available now, more details are available at Imperas.com/ImperasDV.
The free riscvOVPsimPlus package, including the Imperas RISC-V Reference Model, latest test suites, and instruction coverage analysis, including updates for the latest RISC-V ratified specifications is now available on OVPworld at www.OVPworld.org/riscvOVPsimPlus.
Imperas at DVCon 2023
Imperas will participate at DVCon 2023, February 27 through March 2, in San Jose, California. Please stop by and see the latest trends and developments for RISC-V Verification at booth #108. For more details on the presentations, talks, or to request a demo please visit https://www.imperas.com/articles/imperas-dvcon-february-27-march-2-2023.