New Delhi, India, June 4, 2026: Cadence and the Indian Institute of Technology Delhi (IIT Delhi) today announced the IIT Delhi–Cadence Innovation Lab, a multidisciplinary centre of excellence that equips India’s next generation of semiconductor innovators with the same AI‑enabled electronic design automation (EDA) tools and workflows used by industry. The lab advances research, strengthens workforce development and supports pre‑seed startups with a streamlined path to first silicon, aligning with India’s Semiconductor Mission and the Design‑Linked Incentive (DLI) scheme.
Providing proven access to 200+ industry‑grade Cadence solutions across four domains – chip design verification, digital implementation, analog design and system design and analysis – the lab ensures students, researchers and educators learn on the exact tools used in professional environments. By embedding “design with AI” across these workflows, the lab targets step‑change gains in engineering productivity and strengthens the integration of AI in VLSI design.
IIT Delhi has adopted Cadence‑developed courses that combine theory with comprehensive, project‑based labs and assessments, moving beyond a theory‑only model to hands‑on learning with real tools and real‑world problem statements. Guest lectures from Cadence and industry practitioners further align learning with current technology roadmaps and career pathways.
To catalyse research and early-career exploration, the lab is introducing an Early Master’s Research pathway for select fourth‑year undergraduates from IITs and NITs, mentored by Cadence experts and IIT Delhi faculty across multiple research areas. In parallel, the lab’s incubator programme supports pre‑seed startups on a case‑by‑case basis with a low‑cost route to first tape‑out and a working prototype.
“Students at IIT Delhi now use the same AI‑enabled tools they’ll see on day one in industry, closing the gap from classroom to tapeout,” said Alok Jain, Corporate VP and India Managing Director, Cadence. “Pairing industry‑grade technology with project‑based curricula, real‑world challenges and targeted startup support strengthens research relevance and workforce readiness for India’s semiconductor future.”
“The IIT Delhi–Cadence Innovation Lab combines top‑tier academic rigour with cutting‑edge industry tools,” said Prof. Jayadeva, Prof. In-Charge, Cadence-IIT Delhi Innovation Lab. “This partnership will expand research output, prepare students for high‑impact careers and help founders move from ideas to prototypes, supporting the goals of the India Semiconductor Mission and the DLI scheme.”
Looking ahead, the Lab is committed to significantly increasing research output, graduating talent ready to contribute on day one, and cementing high‑impact collaborations that translate academic innovation into industrial outcomes.
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