Silanna Plural Nano High-Performance ADCs are up to 86% Smaller than Competing Devices

SAN DIEGO, CA: November 4th, 2026 – Silanna has launched the Plural™ Nano family of ADCs, the world’s smallest high-performance ADCs.

The family has been created to address the needs of Edge AI and similar advanced applications where board space is strictly limited. At launch, the Nano will offer resolutions from 12- to 16- bits and sample rates from 5 to 250 Msps. The family will be available in a 3.4×3.4 mm (12-bit single/dual, 14- and 16-bit single channel) and a 3.7×3.7 (14- and 16-bit dual channel) 64-ball BGA package.

Competing devices greater than 125 Msps are almost universally sized 9×9 mm or larger, and versus these, the two Nano variants offer footprint reductions of 83% and 86%. Versus competing 125 Msps devices, which are 5×5 mm or larger, the Nano enables footprint reductions of 45% and 54%.

The Nano is the sister chip to Silanna’s Plural, and shares its proprietary factory-configurable architecture, with SKUs defined after fabrication. Traditionally ADC’s specifications are set in silicon, with each SKU requiring its own mask set and production run, a process that introduces significant costs and risks for the manufacturer and has lead times dictated by the fab’s availability.

Silanna’s factory-configurable approach enables devices to be produced in greater volumes, with lower risks. This results in lower prices and shorter lead times versus traditional methods. It also removes the need for niche, unprofitable end-of-life SKUs.

“ADCs are among the larger components on the board and there has long been a need to shrink them. Unfortunately, doing so is not possible with traditional ADC manufacturing – not affordably, at least,” said Randy Wayland, VP of Data Converter Products at Silanna. “This level of footprint reduction is only possible through our Plural architecture, and we’re delighted to have reached sizes that are over 80% smaller than our competitors.”

At launch, 90 12-, 14- and 16- bit ADCs will be available, all with the same feature sets and performance as their full-sized Plural equivalents. The company will also announce additional resolutions and features later this year.

Like the original lineup of Plural ADCs, the Nano family of data converters combines a pipeline ADC core with on-chip reference and clock management circuitry, supports LVDS and CMOS outputs and has an operational temperature range of -40 to +85°C.

The Plural Nano ADC product family and EVKs can be obtained through Silanna’s authorized network of distributors. To register interest, download specifications, and order samples, please visit https://silanna.com/plural-nano-bga/.