While virtual platforms have become the standard approach for processor-based SoC developments, the requirements for quality processor models have never been more critical.
Oxford, United Kingdom, October 30, 2023 — Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Tenstorrent, a next-generation computing company that builds computers for AI, has collaborated with Imperas to make available a model of the Tenstorrent Ascalon processor core as part of the Imperas RISC-V model library. As with other areas of abstraction during the complex SoC design process, software simulation provides a functional representation as a programmer’s view of the hardware – this allows an early-stage evaluation of some design options, firmware, and driver development and offers unique access for debugging and analysis. The models of Tenstorrent IP, available as part of Imperas simulation solutions, supports many time-critical aspects of SoC development and helps address the time-to-market and time-to-volume factors for SoC developers adopting Tenstorrent IP.
Ascalon is a high-performance, scalable RISC-V processor with industry-leading performance efficiency and a highly configurable core that allows it to scale from the Edge to HPC data center/cloud applications. The Imperas model matches Ascalon’s configuration space, including multi and many core options, while offering fast simulation performance for software development of highly complex systems and exploration of different system architectures.
As virtual platforms are now the most common approach to SoC projects with integrated processors, the critical requirement is for quality reference models that accurately represent the configurability of the processor IP core. In addition, for software developers and the wider user community adoption, the models must be compatible with various industry-standard tools and design flows. Many SoC projects are undertaken with teams from multiple locations and often across different corporate departments or even separate firms. Virtual platforms allow for frictionless collaboration across remote teams.
The Imperas model for Ascalon can also integrate within other standard EDA environments, such as SystemC, SystemVerilog, and well-known simulation and emulation tools from Cadence, Siemens EDA, and Synopsys. A hybrid approach is often utilized to combine the Imperas simulation technology with emulation environments to address interim analysis requirements while parts of the RTL of the SoC are still in development.
“The Tenstorrent Ascalon processor is focused on serving the compute requirements of next-generation workloads emerging at the Edge and data center/cloud with the rapid proliferation of AI high-performance applications, including Edge AI and HPC,” said Aniket Saha, VP of Product Strategy at Tenstorrent. “The Imperas model for Ascalon provides a quality model for software development and integration with many popular industry standard flows and EDA tools.”
“Any SoC developer that implements an IP processor core quickly discovers the fundamental interactions between the hardware and software design phases,” said Simon Davidmann, CEO at Imperas Software Ltd. “Now developers using the Tenstorrent Ascalon IP can use the Imperas models as a reference for software development to support the shift-left of project schedules.”
Availability
The Imperas models of the Tenstorrent IP core portfolio are available now via www.OVPworld.org.Imperas RISC-V reference models are also available via approved EDA distribution partners. Please contact Imperas or your preferred EDA supplier to explore this option further.
About OVPworld.org
The Imperas simulation and modeling technology supports over 12 ISAs and 300 processor models. OVPworld (Open Virtual Platforms) is dedicated to making software virtual platforms an accessible and ubiquitous element of embedded software development. As the hardware has gotten more complex, the embedded software has become more complex, requiring new tools. Software virtual prototypes, enabling embedded software simulation, verification, and debugging, are critical to effective embedded software development in the future.
OVP models are typically published under the Apache 2.0 open-source license and include reference platforms, examples, and other collaborative projects from the community of OVP users. OVPworld was established over 10 years ago and has supported thousands of commercial and academic users. Registration is free, as is academic and non-commercial use; commercial users are supported for a 90-day evaluation period.
RISC-V in Space Seminar, November 2, 2023
Tenstorrent is organizing and hosting a seminar in the Denver area aimed at enterprises developing electronic systems and components for space applications, reflecting Colorado’s position as the nation’s second-largest aerospace economy with over 400 active companies. Imperas is excited to be participating in and supporting the seminar. More details can be found at: https://riscv.org/event/risc-v-in-space-seminar/.
RISC-V Summit 2023
Imperas is proud to be a contributing Diamond sponsor for the sixth annual RISC-V Summit, November 7-8, 2023, in San Jose, California. Imperas will showcase solutions for RISC-V processor verification, custom instruction design flows, and software development, including a keynote on RISC-V Processor verification, plus many other activities. More details can be found at: https://riscv.org/event/risc-v-summit-2023/.
About Tenstorrent
Tenstorrent is a next-generation computing company that builds computers for AI. Headquartered in Toronto, Canada, with U.S. offices in Austin, Texas, and Silicon Valley, and global offices in Belgrade, Tokyo, and Bangalore, Tenstorrent brings together experts in the field of computer architecture, ASIC design, advanced systems, and neural network compilers—Hyundai Motor Group, Samsung Catalyst Fund, Eclipse Ventures, and Real Ventures back Tenstorrent. For more information on Tenstorrent, visit www.tenstorrent.com or contact pr@tenstorrent.com.
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